An Economical Alternative to Boundary Scan in Memory Devices (White Paper of the IEEE P1581 Working Group)

IEEE P1581 proposes a standard means of including test features in a memory device, which can collaborate with other 1149.1 Boundary-Scan devices, without requiring boundary scan circuitry, complex controllers or dedicated test pins. The result is a memory device design suitable for printed circuit board (PCB) applications, including those where design for test overhead is often deemed economically unacceptable. Recently developed P1581 test mode entry/exit methods have eliminated the dedicated testpin requirement which was part of the original methodology and still remains as a supplier selected option. Also, the original continuity test circuitry has been joined by an equally robust and simple alternative.